For many applications, and particularly in consumer electronics devices, the large and heavy cathode ray tube (CRT) has been replaced by a flat panel display type, such as a liquid crystal display (LCD), plasma, and organic light emitting diode (OLED). A flat panel display screen contains an array of display elements. Each display element is to receive a signal that represents the picture element (pixel) value to be displayed at that location of the screen. This pixel signal may be applied using a transistor that is coupled to and integrated with the display element. The transistor may act as a switch element. It has a carrier electrode that receives the pixel signal, and a control electrode that receives a gate signal. The gate signal may serve to modulate or turn on and turn off the transistor so as to selectively apply the pixel signal to the coupled display element.
Typically, thousands or millions of copies of the display element and its associated switch element (e.g., an LCD cell and its associated control transistor) are produced in the form of an array, on a substrate such as a plane of glass or other light transparent material. The array is overlaid with a grid of data lines and gate lines. The data lines serve to deliver the pixel signals to the carrier electrodes of the control transistors, and the gate lines serve to apply the gate signals to the control electrodes of the transistors. In other words, each of the data lines is coupled to a respective group of display elements, typically referred to as a column of display elements, while each of the gate lines is coupled to a respective row of display elements. FIG. 1 shows an example of such an arrangement, where the circles in dotted lines represent the display elements (and the data lines and control transistors are not shown).
Although not shown, each data line is coupled to a data line driver circuit that receives control and pixel signals from a signal generator. The latter translates incoming pixel values (for example, red, green and blue pixel values) into data signals (with appropriate timing). The data line driver then performs the needed voltage level shifting to produce a pixel signal with the needed fan-out (current capability).
As to the gate lines, and as seen in FIG. 1, each gate line is coupled to a gate line driver (or simply “gate driver”) having an output Gout. The gate driver receives clock (control) signals GCKA, GCKB from a signal generator (not shown). Each gate driver has a latch stage followed by an output stage that can force its respective gate line to one of two stable voltages in Gout, using an output stage that has a pull-up circuit and a pull-down circuit—see FIG. 2.
The array of display elements are, in most cases, driven in a horizontal or line-by-line scanning fashion: the desired pixel signals for a selected row of display elements are provided on the data lines while at the same time a selected row of display elements is “enabled” by a pulse that is asserted on the associated gate line, by the gate driver of that gate line. The approach is to scan line-by-line or row-by-row in a vertical direction, until the entire display element array has been “filled” with the pixel values of a single image frame. This process may need to be repeated many times per second, to refresh the pixel values in the array.
In some active matrix displays, the gate lines are connected to their respective gate drivers in an interlaced manner, i.e. the locations of the gate drivers alternate between the left and right sides of the display element array as shown in FIG. 1, e.g. the odd numbered lines are driven from the left while the even numbered ones are driven from the right. Also connected to each gate line is a respective pair of switch circuits hc(i)_near and hc(i)_far that together serve as a strong pull-down, to essentially hold the gate line at the level of Vgl; Vgl on a gate line is a voltage source that “disables” the display elements that are controlled by the gate line, thereby preventing pixel values from being loaded into the display elements. To achieve a strong (high current or low impedance) pull-down, the switch circuit hc(i)_near, hc(i)_far may include a relatively large transistor, which may be referred to as a gate line holding transistor. Typically, one column of holding transistors is located at the left side of the display element array as shown, and another column is located at the right side. The control electrodes of the transistors in each column are connected to a respective blanking control line; the two blanking control lines receive the same blanking signal, which is a control signal that is asserted by a display controller (see FIG. 3), during a “blanking interval” portion of a frame display interval. With a display element array that is overlaid with a proximity or touch transducer, forming for example a touch screen, the blanking interval can be used by a touch controller, to read the touch transducer during a “touch interval” portion of the blanking interval.